The present invention relates to semiconductor (integrated circuit) devices and, more particularly, to impedance adjustment circuits and methods for semiconductor devices.
In general, a termination resistor with a resistance, which is equal to the characteristic impedance on a transmission channel, is connected to a receiving or transmitting terminal of a semiconductor device. The termination resistor may reduce reflection of signals transmitted via the transmission channel by substantially matching the impedance of the receiving or transmitting terminal to the characteristic impedance of the transmission channel. Conventionally, a termination resistor is typically installed outside a semiconductor chip. However, in recent years, on-die terminators (ODTs) installed inside a semiconductor chip have replaced termination resistors. A typical ODT requires less power than a termination resistor because it uses a switching circuit that is switched on or off to control current flowing through the ODT. However, a resistance of the ODT may change responsive to changes in process, voltage, and temperature (PVT), and thus, the resistance of the ODT typically is calibrated. An impedance matching circuit for an ODT is described in U.S. Pat. No. 6,690,211.
FIG. 1 is a circuit diagram of a conventional semiconductor device 10 connected to a chip set 30 via a channel 20. The semiconductor device 10 communicates with the chip set 30 via the channel 20. In FIG. 1, Z0 denotes the characteristic impedance of the channel 20, and CP denotes the parasitic impedance on the channel 20. The semiconductor device 10 includes an output driver 11, an input receiver 12, and an internal circuit 13. The output driver 11 includes a pull-up circuit 14 that includes a PMOS transistor P and a resistor R1, and a pull-down circuit 15 that includes an NMOS transistor N and a resistor R2. The output driver 11 outputs data signals, and further acts as an ODT. The impedance at an output node D of the output driver 11 is substantially equalized to the characteristic impedance Z0.
Referring to FIG. 2, when the output driver 11 operates as a driver, one of the PMOS transistor P and the NMOS transistor N is turned on in response to an internal data signal DOUT. In this case, the impedance at the output node D is determined by the impedance of the pull-up circuit 14 or the pull-down circuit 15. Thus, the impedance of the pull-up circuit 14 or the pull-down circuit 15 preferably matches the characteristic impedance Z0. When the output driver 11 operates as an ODT, both the PMOS transistor P and the NMOS transistor N are turned on. In this case, the impedance at the output node D is determined by the parallel combination of the impedances of the pull-up circuit 14 and the pull-down circuit 15. Preferably, the parallel combination of the impedances of the pull-up circuit 14 and the pull-down circuit 15 matches the characteristic impedance Z0. Conventionally, VDD/2 is a reference voltage used to calibrate the impedance of the output driver 11. Specifically, when one of the PMOS transistor P and the NMOS transistor N is turned on, the impedances of the pull-up circuit 14 and the pull-down circuit 15 are calibrated to adjust a voltage Vout at the output node D to VDD/2. The voltage Vout generated at the output node D is generally not VDD/2 when the output driver 11 operates.
When the internal data signal DOUT is at a logic high level, the PMOS transistor P is turned off and the NMOS transistor N is turned on. A voltage Vout1 generated at an output node D1 of the output driver 11 is given by:
                              Vout          ⁢                                          ⁢          1                =                  Vout          ⁢                                          ⁢          2          ×                                    impedance              ⁢                                                          ⁢              of              ⁢                                                          ⁢              pull              ⁢                              -                            ⁢              down              ⁢                                                          ⁢              circuit              ⁢                                                                                ⁢                                                                              ⁢              15                                                      sum                ⁢                                                                  ⁢                of                ⁢                                                                  ⁢                impedance                ⁢                                                                  ⁢                of                ⁢                                                                                          ⁢                                                                                        ⁢                pull                ⁢                                  -                                ⁢                downcircuit                ⁢                                                                  ⁢                15                            ,                              and                ⁢                                                                  ⁢                parallel                ⁢                                                                  ⁢                sum                ⁢                                                                                          ⁢                                                                                        ⁢                of                ⁢                                                                  ⁢                impedances                ⁢                                                                  ⁢                R3                ⁢                                                                  ⁢                and                ⁢                                                                  ⁢                R                ⁢                                                                  ⁢                4                ⁢                                                                  ⁢                of                ⁢                                                                  ⁢                terminator                ⁢                                                                  ⁢                31                                                                        (        1        )            When the internal data signal DOUT is at a logic high level, the generated voltage Vout1 obtained from Equation (1) is 0.3 V.
When the internal data signal DOUT is at logic low level, the PMOS transistor P is turned on and the NMOS transistor N is turned off. The voltage Vout1 generated at the output node D1 is given by:
                              Vout          ⁢                                          ⁢          1                =                  [                                    (                              VDD                -                                  Vout                  ⁢                                                                          ⁢                  2                                            )                        +                                                                                                                                             parallel                        ⁢                                                                                                  ⁢                        sum                        ⁢                                                                                                  ⁢                        of                        ⁢                                                                                                                                  ⁢                                                                                                                                ⁢                        impedances                        ⁢                                                                                                  ⁢                        R                        ⁢                                                                                                  ⁢                        3                                                                                                                                                and                        ⁢                                                                                                  ⁢                        R                        ⁢                                                                                                  ⁢                        4                        ⁢                                                                                                  ⁢                        of                        ⁢                                                                                                  ⁢                        terminator                        ⁢                                                                                                                                  ⁢                                                                                                                                ⁢                        31                                                                                                                                                                                                          sum                          ⁢                                                                                                          ⁢                          of                          ⁢                                                                                                          ⁢                          impedance                          ⁢                                                                                                          ⁢                          of                          ⁢                                                                                                          ⁢                          pull                          ⁢                                                      -                                                    ⁢                                                                                                          ⁢                          upcircuit                          ⁢                                                                                                          ⁢                          14                                                ,                                                                                                                                                and                        ⁢                                                                                                  ⁢                        parallel                        ⁢                                                                                                                                  ⁢                                                                                                                                ⁢                        sum                        ⁢                                                                                                  ⁢                        of                        ⁢                                                                                                  ⁢                        impedances                                                                                                                                                R                        ⁢                                                                                                  ⁢                        3                        ⁢                                                                                                  ⁢                        and                        ⁢                                                                                                  ⁢                        R                        ⁢                                                                                                  ⁢                        4                        ⁢                                                                                                  ⁢                        of                        ⁢                                                                                                  ⁢                        terminator                        ⁢                                                                                                  ⁢                        31                                                                                                        ]                        +                                                         Vout                ⁢                                                                  ⁢                2                                                                        (        2        )            When the internal data signal DOUT is at a logic low level, the generated voltage Vout1 obtained from Equation (2) is 1.2 V.
As described above, when the output driver 11 operates, the voltage Vout1 generated at the output node D1 is 0.3 V or 1.2 V, that is, the voltage Vout1 is not 0.75 V, i.e., VDD/2. Accordingly, when the output driver 11, the impedance of which is calibrated using VDD/2 as the reference voltage, operates, the I-V characteristics of the output driver 11 may deteriorate.
FIG. 3A is a graph illustrating the operating characteristics of output drivers whose impedances are calibrated using a conventional method. In FIG. 3A, curves A1 through A3 indicate the I-V characteristics of the pull-down circuits of output drivers whose impedances are calibrated using the conventional method, and curves B1 through B3 indicate the I-V characteristics of the pull-up circuits of the output drivers whose impedances are calibrated using the conventional method. Also, the curves A1 and B1 illustrate the I-V characteristics of the output drivers with the best operating conditions, the curves A3 and B3 illustrates the I-V characteristics of the output drivers with the worst operating conditions. The curves A2 and B2 illustrate the I-V characteristics of the output drivers with the med-level operating conditions. Because the impedances of the output drivers are calibrated using the conventional method, i.e., using the reference voltage, the curves A1 through A3 intersect when VDD/2, e.g., 0.75V, is used, and the curves B1 through B3 also intersect when VDD/2, e.g., 0.75V, is used.
FIG. 3B illustrates the result of a simulation in which the impedances of output drivers were calibrated using a conventional method. In detail, FIG. 3B illustrates the skew and aperture of a transmitted signal according to the value of the parasitic capacitance CP at the channel 20 when output voltages of the output drivers are VDD/2, e.g., 0.75V, and the impedances of the pull-down circuits with I-V characteristics indicated by the curves A1 through A3 of FIG. 3A are adjusted to 40 Ω. For convenience, the pull-down circuits that have the I-V characteristics indicated by the curves A1 through A3 will be referred to as pull-down circuits A1 through A3, respectively. When the output voltages of the output drivers are 0.3 V, the impedances of the pull-down circuits A1 through A3 are 38 Ω, 36 Ω, and 32 Ω, respectively. Referring to FIG. 3B, an increase in the parasitic capacitance CP increases the skew of the pull-down circuits A1 through A3 but reduces the apertures thereof. In the simulation, variations in the skews of the pull-down circuits A1 through A3 were 1 ps, 3 ps, 2 ps, and 1 ps, when the parasitic capacitances CP were 2.0 pF, 2.5 pF, 3.0 pF, and 3.5 pF, respectively. That is, the variations were less than 4 ps. Also, variations in the apertures of the pull-down circuits A1 through A3 were 9 mV, 13 mV, 14 mV, and 12 mV when the parasitic capacitances CP were 2.0 pF, 2.5 pF, 3.0 pF, and 3.5 pF, respectively. That is, the variations were less than 15 mV. The impedance of the output driver is preferably calibrated such that variations in the skews and apertures of the output drivers are reduced regardless of the I-V conditions of the output drivers.
As described above, conventionally, the impedance of an output driver is calibrated using a reference voltage that is not related to an output voltage generated when the output driver operates, which may thereby increase variations in the skew and aperture of a transmitted signal and deteriorate the operating performance of the output driver.